The 7476 JK Flip Flop Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs. 7476 IC contains two independent positive pulse triggered J-K flip-flops with complementary outputs.The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave.
The logic state of J and K inputs must not be allowed to change while the clock is HIGH. The data is transferred to the outputs on the falling edge of the clock pulse. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs .The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and DirectClear inputs. These dual flip-flops are designed so that when the clockgoes HIGH, the inputs are enabled and data will be accepted. The Logic Levelof the J and K inputs will perform according to the Truth Table as long as minimumset-up times are observed. Input data is transferred to the outputs on theHIGH-to-LOW clock transitions
Features of HD74LS76AP:
- Recommended Voltage Supply Range:4.75-5.25V
- Maximum Supply Voltage:7V
- Maximum Input Voltage:7V
- Maximum Power Dissipation:400mW
- Storage temperature : –65 to +150 °C